Reed-Solomon Erasure Codec Design Using Vivado High-Level Synthesis Application Note (XAPP1273)

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This application note focuses on the design of an erasure codec using the Xilinx® Vivado® High-Level Synthesis (HLS) tool, which takes the source code in C programming language and generates highly efficient synthesizable Verilog or VHDL code for a Kintex® UltraScaleTM FPGA. When there is a need to change erasure code parameters, for example, the generator matrix definition or erasure code rate, only slight modification to the C header files is needed. The example Reed-Solomon erasure codec has a generic architecture from which other types of erasure codecs can be obtained by modifying the C source code.

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تاریخ انتشار 2009